MAX1183ECM+TD【PDF 2/18 页】IC ADC 10BIT 40MSPS DL 48-TQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录2008

1页 [2页]3页 4页 5页 6页

MAX1183

Detailed Description

The MAX1183 uses a nine-stage, fully differential,

pipelined architecture (Figure 1) that allows for high-

speed conversion while minimizing power consump-

tion. Samples taken at the inputs move progressively

through the pipeline stages every half-clock cycle.

Including the delay through the output latch, the total

clock-cycle latency is five clock cycles.

One-and-a-half bit (2-comparator) flash ADCs convert

the held-input voltages into a digital code. The digital-

to-analog converters (DACs) convert the digitized

results back into analog voltages, which are then sub-

tracted from the original held-input signals. The resulting

error signals are then multiplied by two, and the residues

are passed along to the next pipeline stages where the

process is repeated until the signals have been

processed by all nine stages. Digital error correction

compensates for ADC comparator offsets in each of

these pipeline stages and ensures no missing codes.

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________

T/H

VOUT

FLASH

ADC

DAC

1.5 BITS

VINA

VIN

STAGE 1

STAGE 2

D9A–D0A

VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)

VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)

DIGITAL CORRECTION LOGIC

STAGE 8

STAGE 9

2-BIT FLASH

ADC

T/H

VOUT

FLASH

ADC

DAC

1.5 BITS

VINB

VIN

STAGE 1

STAGE 2

D9B–D0B

DIGITAL CORRECTION LOGIC

STAGE 8

STAGE 9

2-BIT FLASH

ADC

T/H

Figure 1. Pipelined Architecture—Stage Blocks

Pin Description (continued)

PIN

NAME

FUNCTION

D6A

Three-State Digital Output, Bit 6, Channel A

D7A

Three-State Digital Output, Bit 7, Channel A

D8A

Three-State Digital Output, Bit 8, Channel A

D9A

Three-State Digital Output, Bit 9 (MSB), Channel A

REFOUT

Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor

divider.

REFIN

Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a >1nF capacitor.

REFP

Positive Reference Input/Output. Conversion range is

± (VREFP - VREFN).

Bypass to GND with a > 0.1F capacitor.

REFN

Negative Reference Input/Output. Conversion range is

± (VREFP - VREFN).

Bypass to GND with a > 0.1F capacitor.

—

Exposed Pad. Connect to analog ground.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式